A new approach of Margin Tester breaks new ground as a specialized testing tool for design and validation of PCIe Gen 3 and Gen 4 motherboards, add-in cards, and system designs. While PCIe testing normally requires complex test systems and engineers with deep expertise and knowledge, this new approach enables engineers at all levels of experience to evaluate the health of transmitter (Tx) and receiver (Rx) links faster than ever, greatly reducing time to market and cost of ownership. This new approach supports the majority of common PCIe form factors, including CEM, M.2, U.2, and U.3, with testing capabilities of up to 16 lanes across PCIe presets 0-9, using a single standard connector.
Spreker volgt, CN Rood
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