Most FPGA development time is spent on verification. The verification process consists of timing analysis, internal and external simulation, formal verification, power and signal integrity analysis and in-system testing. This presentation will focus on Static Timing Analysis also called STA.
How do you know your design meet your timing requirements? STA is the answer. Every device path in a design must be analyzed with respect to timing specifications/requirements. The purpose of STA is to catch timing related errors faster and easier than gate-level simulation and board testing. To do this the designer must enter the proper timing requirements and exceptions, also called timing constraints. These timing constraints will guide the place and route tools and must be verified.
We will cover some basic STA constraints, explain how to constrain source and system synchronous IO interface, describe clock domain crossing and when to use a generated and/or virtual clock. This presentation on STA is not only for novice but also as a refresher for advanced users.
Frank de Bont, Core|Vision