{"id":66125,"date":"2025-04-23T16:25:17","date_gmt":"2025-04-23T14:25:17","guid":{"rendered":"https:\/\/fhi.nl\/nieuws\/designing-better-pcbs-using-minimum-clearances-wisely-2\/"},"modified":"2025-04-23T16:25:17","modified_gmt":"2025-04-23T14:25:17","slug":"designing-better-pcbs-using-minimum-clearances-wisely-2","status":"publish","type":"news","link":"https:\/\/fhi.nl\/en\/news\/designing-better-pcbs-using-minimum-clearances-wisely-2\/","title":{"rendered":"Designing better PCBs: using minimum clearances wisely"},"content":{"rendered":"\n
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\n\t\t\t\t\tDesigning better PCBs: using minimum clearances wisely\t\t\t\t<\/h1>\n\n\t\t\t\t
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On a recent visit to our factories in Eger I asked the PCB manufacturing manager, J\u00f3zsef Lengyel, and his team, what are the top ten customer-data issues that they experience. The answer was unanimous and immediate: designers using the tightest design rules on the entire board<\/em> instead of just to the specific places where they are absolutely required. I then asked what the other nine issues were, to which I got an unexpected response: the same answer!<\/p>\n\n\n\n

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Design Rules: One Size Does Not Fit All<\/h5>\n\n\n\n
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When we layout a board we usually start by focusing on the hard parts \u2013 fine-pitch QFNs, BGAs, strict connector placements, etc. \u2013 which will determine the tightest minimum track-widths and clearances that we can get away with, and eventually determine the manufacturing costs. At some point we\u2019ll look at PCB manufacturers\u2019 minimum clearances \u2013 track-to-track, pad-to-track, etc. \u2013 for our board, and set the EDA tool\u2019s DRC accordingly. These settings will be, most often, applied to the entire board, which means that these minimum clearances will appear throughout the board, even where there\u2019s plenty of space<\/em>, rather than only where needed.<\/p>\n\n\n\n

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Now, as designers we assume that this isn\u2019t a problem because we\u2019re paying for those settings for the entire board<\/em>, so the manufacturer can, and should, just deal with it. It turns out that this is a problem for both the manufacturer and<\/em> the designer, in the long run.<\/p>\n\n\n\n

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Why Overusing Minimum Clearances Hurts Everyone<\/h5>\n\n\n\n
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For the manufacturer, there are now many more potential manufacturing fault points throughout the board that they need to identify, check, tweak, and, in some cases, report back as issues to be fixed by the designer, causing delays. Then the reality of manufacturing kicks in: with decreasing clearances the number of defects increase. This ends up affecting manufacturing times and cost, and if we consider the operation as a whole, increases costs for everyone<\/em>.<\/p>\n\n\n\n

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For the designer, this amount of difficult spots may be an issue later during a production run: manufacturing three boards is quite a different matter than manufacturing 3,000! Switching to a different manufacturer is another potential pain-point since they might not be able to deal with these issues as well as the previous one, or make different decisions about what to do with minor problems. All this may decrease yield and quality, increase cost, and affect delivery times.<\/p>\n\n\n\n

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So here\u2019s the tip<\/strong>. Use the smallest DRC settings only where absolutely necessary and relax them everywhere else. Some EDA tools won\u2019t make this straightforward, but there\u2019s usually a way to arm-twist them into being helpful with this. In any case, we should think of minimum clearance spots in the same way that we think of number of layers, component count, or BoM line-items: fewer is better<\/em>! It will make you a better circuit-board designer, and, as a bonus, manufacturers will love you.<\/p>\n\n\n\n

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A sliver between tracks during AOI: example of a defect with increasing probability when track spacing reduces.<\/em><\/figcaption><\/figure>\n\n\n\n
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Many thanks to Geert Willems (imec, EDM Forum<\/strong><\/a>) for his comments on drafts of this article.<\/p>\n\n\n\n

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Further reading:<\/p>\n\n\n\n

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