Cadence Technology on Tour: Custom IC – Analog IP Verification
Best practices and methodologies for verifying DAC/ADCs and PLLs with SPICE accuracy in minutes and hours
How do you verify the functionality of your data converters (ADCs and DACs) and PLLs against performance specifications? You’ll need to consider your architecture, impact of advanced technology nodes, device noise, post-layout parasitic, device mismatch, and design integration.
This full-day seminar featuring technical presentations will help to tackle your verification challenges. You’ll get an overview of data converter and PLL design architecture, plus learn best practices, verification plans, methodologies, and techniques using the production-proven Cadence® Spectre® simulation technologies in the Virtuoso® Analog Design Environment (ADE). You’ll gain invaluable insight from our analog IP designers and simulation technology R&D experts on how to verify today’s complex data converters and PLL designs more productively and profitably. Topics covered include:
- Design specification-driven simulation
- Linear phase-domain modeling
- Efficient Spice accurate and high-performance simulation
- Metastability characterization
- Effective number of bits (ENOB) verification
Space is limited. Register now!