Next generation digital interface standards (serial, memory, display etc.) are pushing the limits of today’s compliance and debug tools posing several high speed Tx and Rx design challenges including
– Limited signal access due to smaller device geometries
– Bus behavior with new power-saving schemes
– Validating new signal encoding and equalization capability in signaling interfaces
– So many electrical validation tests, so little time!
In the presentation automated measurement suites that speed up PHY validation cycles and ensure consistency will be provided. Speed up debugging with tools like Protocol Decoding and Visual Trigger when compliance measurements fail. Identify jitter & noise from sources such as crosstalk or other multi-lane noise coupling.
John Marrinan, Tektronix on behalf of C.N. Rood