Partial HDI in Practice: FPGA High-Speed Routing Designer Insight

Designer Insights #1: Real projects. Real challenges. Real decisions.

What does it take to make a high-speed FPGA design work first time under tight space constraints and without overengineering the PCB?

In our first Designer Insight, Frank, CID+ (Certified Interconnect Designer), shares how he approached a dense video-signal layout where routing space was limited, signal integrity critical and backdrilling not an option.

Instead of going full HDI, he chose a more targeted path: Partial HDI, applied only where it added real value on an 8-layer pooled buildup from Eurocircuits. By carefully managing layer transitions under a shared reference plane and using microvias strategically, he created additional routing space, avoided unnecessary complexity and achieved clean signal behavior.

A key moment came during the PCB/PCBA Visualizer review: a deviation in BGA pad sizes was detected and corrected early, preventing potential production issues.

Result: a fast, cost-efficient prototype that worked right away.

Your experience matters

This is the start of our Designer Insights series built on real-world challenges and practical engineering decisions.

Have you solved a tricky layout, manufacturing, or data challenge?
Share your insight with the community, anonymously or with your name/company.

Because the best solutions are the ones engineers learn from each other.

The Eurocircuits Team