UVM is worth the investment

As your FPGA and chip designs become more complex, the verification of these designs also becomes more complex. The Universal Verification Methodology (UVM) standard was created to verify these designs – a powerful, reusable and scalable verification method. It offers advanced features such as constrained-random testing, functional coverage and automatic verification, leading to higher quality and reliability of your designs.

UVM has become the de facto standard for verification and is supported by many simulators. It seems good, but when you dive into it there are still some hurdles to overcome. New techniques have to be learned and this may be the first encounter with SystemVerilog, and that could be daunting. And yet the use of UVM can yield a lot. That UVM is really worth the investment is shown in this presentation.

Speaker: Paul Eijkelkamp – Dizain-Sync

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