UVM is worth the investment

As your FPGA and chip designs become more complex, so does the verification of these designs. The Universal Verification Methodology (UVM) standard was created for the verification of these designs – a powerful, reusable and scalable verification method. It provides advanced features such as constrained-random testing, functional coverage and automatic verification. This leads to higher quality and reliability of your designs.

UVM has become the de facto standard for verification and is supported by many simulators. Seems good, but when you dive in there are still some hurdles to overcome.

You have to learn new techniques and this may be your first encounter with SystemVerilog. That could be daunting, while the use of UVM can yield a lot. That UVM is really worth the investment, we show in this presentation.

Speaker: Paul Eijkelkamp – Dizain-Sync

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