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The complexity of FPGA design process is increased by the fact that in practice various languages and tools are used, such as Matlab, C++, VHDL. Furthermore, there are different teams of specialists, each working in their own language. This often leads to misunderstandings, which in turn lead to delays in the design process.
Clash is a modern environment for FPGA design in which one single language is used at all stages of the design process, from the initial model of an application to the final implementation on an FPGA. Along the way, each step can be tested in a cycle accurate way, and there is powerful support for verification such as a strong type checking mechanism. Consequently, a design process proceeds considerably faster, leading to substantially shorter time-to-market.
During the talk we will discuss these issues.
Jan Kuper, QBayLogic BV
Klik hier voor de PDF-versie van de presentatie.