The benefits of model-based FPGA design

Designing FPGAs – field-programmable gate arrays – is a complex task. With a design environment where the same language is used at all levels, QBayLogic wants to accelerate and simplify the development process. The functional system Clash has been developed for this purpose. Jan Kuper from QBayLogic will tell you more about this during the hardware design webinars.

 By: Dimitri Reijerman

Kuper briefly explains what FPGAs, a circuit of programmable logic components, can do exactly: “FPGAs are processors where the calculations are done directly in the hardware. In fact, you can organize the digital hardware in such a way that you configure it for a specific task. They are a factor of ten to a hundred faster than CPUs and consume much less energy. The disadvantage of an FPGA, at least up to now, is that programming them is not easy. You do not program them in the traditional sense, where you describe everything step by step. On an FPGA you describe a structure.”

He continues: “If you want to describe such a structure, you have to tell an FPGA – in principle – which wire is connected to which transistor and how you connect all the circuits together. That is a huge list, up to billions of connections. So that has to be done by an abstract language that can describe it.”

In the FPGA world, other languages are therefore used, says Kuper: “Traditionally, these are languages such as VHDL and Verilog. But these languages are quite flow-level, which means it takes a lot of work to get everything up and running. You also need very specialized people and it is difficult to run simulations with languages such as VHDL.”

“So everyone is looking for higher abstraction languages on top of VHDL and Verilog. The world approaches programming an FPGA in the way we once learned it. Like C, C++, Java, you name it. But these languages are based on programming a normal processor.”

Haskell & Clash

A combination of Haskell and the Clash environment developed for FPGAs should help companies with this: “We do it with a different type of language with which you can directly describe structure, so a functional programming language”, Kuper explains. “We work with Haskell. That language looks at a problem in a more abstract way and is more suitable for an FPGA. In research at the UT, a compiler was built with which the functional code can be written to VHDL and translated to VHDL, so that the FPGA can be configured. This compiler has been further developed into a total package Clash. That is also where QBayLogic came from. Because we believe this is the way to look at an FPGA.”

During his lecture, Kuper will explain the specific benefits of Clash. Would you like to this webinar visit for free? Register now.